SN74LVC1G125 (ACTIVE)
Single Bus Buffer Gate With 3-State Outputs
Description
This bus buffer gate is designed for 1.65-V to 5.5-V VCCoperation.
The SN74LVC1G125 device is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high.
The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating
Features
- Available in the Ultra Small 0.64-mm2
Package (DPW) With 0.5-mm Pitch
- Supports 5-V VCC Operation
- Inputs Accept Voltages to 5.5 V
- Provides Down Translation to VCC
- Max tpd of 3.7 ns at 3.3 V
- Low Power Consumption, 10-μA Max ICC
DESCRIPTION/ORDERING INFORMATION
SN74LVC1G125 SINGLE BUS BUFFER GATE WITH 3-STATE OUTPUT SCES223O–APRIL 1999–REVISED FEBRUARY 2007
• Available in the Texas Instruments
• I off Supports Partial-Power-Down Mode NanoStar™ and NanoFree™ Packages Operation
• Supports 5-V VCC Operation
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• Inputs Accept Voltages to 5.5 V • Max t
• ESD Protection Exceeds JESD 22 pd of 3.7 ns at 3.3 V
– 2000-V Human-Body Model (A114-A)
• Low Power Consumption, 10-µA Max I CC
– 200-V Machine Model (A115-A)
• ±24-mA Output Drive at 3.3 V
– 1000-V Charged-Device Model (C101)
This bus buffer gate is designed for 1.65-V to 5.5-V VCC operation. The SN74LVC1G125 is a single line driver with a 3-state output. The output is disabled when the output-enable (OE) input is high. NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using I off . The I off circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
| ABSOLUTE MAXIMUM RATINGS(1) |
|
Supply voltage, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . 7 V
Input voltage, VI: ’LS. . . . . . . . . . . . . . . . . . . . . . . . 7 V
L’S . . . . . . . . . . . .. . . 5.5 V
Off-state output voltage . . . . . . . . . . . . . 5.5 V
Package thermal impedance, θJA (see Note 2): DB package . . . . . . . . . . . . . 70 C/W
DW package . . . . . . . . . . . . . . . . . . . 58 °C/W
N package . . . . . . . . . . . . . . . . . . . . . . 69 °C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . .60 °C/W
Storage temperature range, Tstg . . . . . . –65°C to 150°C
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